The present invention relates generally to using a variable interconnect geometry for first/second level interconnects in electronic packages, and methods for implementing the same.
Power and latency are fast becoming major bottlenecks in the design of high performance microprocessors and computers. Power relates to both consumption and dissipation, and therefore, effective power distribution design and thermal management solutions are required. Latency is caused by the global interconnects on an integrated circuit (IC) that span at least half a chip edge due to the RC and transmission line delay. Limits to chip power dissipation and power density and limits on hyper-pipelining in microprocessors threaten to impede the exponential growth in microprocessor performance. In contrast, multi-core processors can continue to provide a historical performance growth on most consumer and business applications provided that the power efficiency of the cores stays within reasonable power budgets. To sustain the dramatic performance growth, a rapid increase in the number of cores per die and a corresponding growth in off-chip bandwidth are required. Furthermore, to reduce the RC and transmission line delay, low-K dielectric/Cu and ultra-low-K dielectric/Cu interconnects on silicon will become increasingly common. In such ICs, the thermo-mechanical stresses induced by the chip-to-substrate interconnects could crack or delaminate the dielectric material causing reliability problems. On the other hand using a compliant structure as an off-chip interconnect allows for isolation of the die from the substrate. Therefore they would not crack or delaminate the low-K dielectric. However a compliant structure would have lower electrical performance. To address this, keeping in perspective the mechanical requirements, I/O customization could be utilized. This would allow off-chip interconnects to address the increasing demands on their electrical performance.
Conventional electronic packages typically include interconnects that are nearly identical in shape and size from the center to the edge. Flip chip solder bumps, BGA solder balls and CSP interconnects are some of the examples. However, as one moves from the center to the edge of a package or a chip, the differential expansion due to coefficient of thermal expansion (CTE) mismatch (between chip and board or chip and interposer/substrate or package and board) increases. Hence, the choice of the interconnect design is such that the interconnect at the furthest distance from the center of the die, where the differential displacement between the die and the substrate due to CTE mismatch is maximum, has sufficient fatigue life and will not delaminate or crack the low-K dielectric in the die.
It would be desirable to have improved packaging techniques and methods and utilize a step wise or continuous variation of interconnect geometry in an electronic package. This would improve the electrical performance of electronic packages without compromising on mechanical reliability.